1. Field of the Invention
This invention relates to systems, methods, and design structures for current mode logic differential driver ESD protection circuitry.
2. Description of Background
For high-speed differential operation in the GHz range, current mode logic (CML) drivers are typically used for their large attainable bandwidth. These are simple resistively loaded differential amplifiers.
As technology scales supply voltage, transistor threshold voltage, breakdown voltage reduces. The lower breakdown voltage of the devices makes them susceptible to the electrostatic discharge (ESD) stress. Lower threshold voltages of the transistors make them conduct large current at small overdrive voltages. This current can exceed the current limit of the salicided driver transistor, leading to failures.
Recently, driver NFETs failure was discovered in the CML driver topology during pad-to-pad or pin-to-pin electrostatic discharge (ESD) stress. It has been observed that during pad-to-pad ESD stress, one of the driver transistors of the CML driver turns on putting the entire ESD stress across its partner (the other driver transistor of the CML driver). In a CML driver structure, an ESD zap is applied at one pad and ground connection is applied to the other pad to create an ESD stress test. In operation, one of the drivers of the CML driver structure turns on discharging the current mode (CM) node of the CML driver to 0V. This puts most of the entire ESD stress on its partner. This causes drain-source short on the partner driver transistor, leading to ESD failures.